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SY89835U
2.5V, 2GHz (3.2 Gbps) Ultra-Precision, Differential 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input
General Description
The SY89835U is a 2.5V, high-speed 2GHz differential Low Voltage Differential Swing (LVDS) 1:2 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 20ps over supply voltage and temperature. A unique Fail-Safe Input (FSI) protection prevents metastable conditions when no signal is present or when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops sufficiently below 100 mV). The SY89835U is part of Micrel's high-speed clock synchronization family. For applications that require a different I/O combination, consult Micrel's web site, and choose from a comprehensive product line of highspeed, low-skew fanout buffers, translators and clock generators. Data sheets and support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge(R)
Features
* Guaranteed AC performance over temperature and voltage: - DC-to > 3.2Gbps throughput - 210ps typical propagation delay (IN-to-Q) - <20ps within-device skew - <150ps rise/fall times * Fail Safe Input - Prevents outputs from oscillating * Ultra-low jitter design - <1psRMS cycle-to-cycle jitter - <10psPP total jitter - <1psRMS random jitter - <10psPP deterministic jitter * High-speed LVDS outputs * 2.5V 5% power supply operation * Industrial temperature range: -40C to +85C * Available in 8-pin (2mm x 2mm) MLFTM package
Functional Block Diagram
Applications
* * * * Clock or data distribution SONET clock or data distribution Fibre Channel clock or data distribution Gigabit Ethernet clock or data distribution
Markets
* * * * * DataCom Telecom Storage ATE Precision test and measurement
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
February 2006
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SY89835U
Ordering Information(1)
Part Number SY89835UMG SY89835UMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
Package Type MLF-8 MLF-8
Operating Range Industrial Industrial
Package Marking 835 with Pb-Free bar-line indicator 835 with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
8-Pin MLFTM (MLF-8)
Pin Description
Pin Number 1 2, 3 Pin Name VCC IN, /IN Pin Function Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitor and place as close to VCC pin as possible. Power supply tolerance is 5%. Differential Inputs: This input pair is the differential signal input to the device. Input accepts DC-Coupled differential signals as small as 100mV (200mVPP). The input is internally terminated with 100 between IN and /IN. If the input swing falls below a certain threshold (typically 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. Please refer to the "Input Interface Applications" section for more details. Ground. GND pins and exposed pad must be connected to the most negative potential of the device ground. Differential Outputs (LVDS): Normally terminated with 100 across the pair (Q, /Q). See "LVDS Outputs" section, Figure 2a.
4 5, 6 7, 8
GND /Q1, Q1 /Q0, Q0
Truth Table
IN 0 1 /IN 1 0 Q 0 1 /Q 1 0
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SY89835U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................... -0.5V to +4.0V Input Voltage (VIN) ............................ -0.5V to VCC +0.3V LVDS Output Current (IOUT)..................................10mA Input Current Source or Sink Current on (IN, /IN) ...............50mA Lead Temperature (soldering, 20sec.) .................. 260C Storage Temperature (Ts) ....................-65C to +150C
Operating Ratings(2)
Supply Voltage (VIN)...................... +2.375V to +2.635V Ambient Temperature (TA) ................... -40C to +85C Package Thermal Resistance(3) MLFTM Still-air (JA) ........................................... 93C/W Junction-to-board (JB) ......................... 32C/W
DC Electrical Characteristics(4)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RDIFF_IN VIH VIL VIN VDIFF_IN VIN_FSI Parameter Power Supply Voltage Range Power Supply Current Differential Input Resistance (IN-to-/IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing (|IN - /IN|) Input Voltage Threshold that Triggers FSI see Figure 2c see Figure 2d No load, max. VCC 90 1.2 0 0.1 0.2 30 100 Condition Min 2.375 Typ 2.5 50 100 Max 2.625 70 110 VCC VIH-0.1 VCC Units V mA V V V V mV
LVDS Outputs DC Electrical Characteristics(4)
VCC = +2.5V 5%, RL = 100 across the outputs; TA = -40C to +85C, unless otherwise stated.
Symbol VOUT VDIFF_OUT VOCM VOCM
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB and JA values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Output Voltage Swing Differential Output Voltage Swing Output Common Mode Voltage Change in Common Mode Voltage
Condition See Figure 2c See Figure 2d
Min 250 500 1.125 -50
Typ 325 650 1.20
Max
Units mV mV
1.275 50
V mV
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SY89835U
AC Electrical Characteristics(5)
VCC = +2.5V 5%, RL = 100 across the outputs; TA = -40C to +85C, unless otherwise stated.
Symbol fMAX tPD tSkew tJitter Parameter Maximum Frequency Propagation Delay Within Device Skew Part-to-Part Skew Data Clock tr, tf Random Jitter Deterministic Jitter Cycle-to-Cycle Jitter Total Jitter Output Rise/Fall Times (20% to 80%) Duty Cycle
Notes: 5. 6. 7. 8. 9. High-frequency AC parameters are guaranteed by design and characterization. Within device skew is measured between two different outputs under identical input transitions. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs. Random jitter is measured with a K28.7 pattern, measured at fMAX. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 -1 PRBS pattern.
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Condition VOUT > 200mV IN-to-Q VIN: 100mV-200mV > 200mV Note 6 Note 7 Note 8 Note 9 Note 10 Note 11 At full output swing. Differential I/O NRZ Data Clock
Min 3.2 2.0 150 100
Typ 3.0 300 210 5
Max
Units Gbps GHz
500 400 20 200 1 10 1 10
ps ps ps psRMS psPP psRMS psPP ps %
40 47
75
150 53
10. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn -Tn+1, where T is the time between rising edges of the output signal. 11. Total jitter definition: with an ideal clock input frequency of fMAX (device), no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value.
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SY89835U metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions. Please note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend upon the rise and fall time of the input signal and on its amplitude. Refer to "Typical Operating Characteristics" for detailed information.
Functional Description
Fail-Safe Input (FSI) The input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mVPK (200mVPP). Input Clock Failure Case If the input clock fails to a floating, static, or extremely low signal swing, the FSI function will eliminate a
Timing Diagrams
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SY89835U
Typical Characteristics
VCC = 2.5V, GND = 0V, VIN = 100mV, RL = 100 across the outputs, TA = 25C, unless otherwise stated.
February 2006
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SY89835U
Functional Characteristics
VCC = 2.5V, GND = 0V, VIN = 100mV, RL = 100 across the outputs, TA = 25C, unless otherwise stated.
February 2006
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SY89835U
Input Stage
Figure 2a. LVDS Differential Measurement
Figure 1. Simplified Differential Input Buffer
LVDS Outputs
LVDS specifies a small swing of 325mV typical, on a nominal 1.20V common mode above ground. The common mode voltage has tight limits to permit large variations in ground noise between an LVDS driver and receiver. These outputs can drive AC- or DCcoupled differential signals. The SY89835U can drive long lengths of coaxial cables and FR4 traces. Table 1 below shows typical lengths of cables driven at different clock and data rates.
Clock/Data Rate 100MHz 622MHz 1.25Gbps 2.50Gbps Coaxial Cable (1) Length 4.5m 3.5m 3.8m 3.3m FR4 Cable Length(2) 1.40m 0.85m 0.80m 0.50m
Figure 2b. LVDS Common Mode Measurement
Figure 2c. Single-Ended Swing
Table 1. Typical Lengths of Coaxial and FR4 Traces
Notes: 1. Specifications for the center conductor of the coaxial cables used are "19 1/19 spcw OD .037 inch 0.001". These are 1m cables, p/n SB-142 manufactured by Harbour Industries. www.harbourind.com. The FR4 traces are 6.25mil wide and 6mil thick. Horizontal distance between adjacent traces is 7.75mil. These traces are fabricated on a Molex GBX Reference Backplane. www.molex.com.
Figure 2d. Differential Swing
2.
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SY89835U
Input Interface Applications
Figure 3. LVDS Input Interface
Related Product and Support Documents
Part Number SY89542U SY89543L SY89544U Function 2.5V, 3.2Gbps Dual, Differential 2:1 LVDS Multiplexer with Internal Termination 3.3V, 3.2Gbps Dual, Differential 2:1 LVDS Multiplexer with Internal Termination 2.5V, 3.2Gbps Differential 4:1 LVDS Multiplexer with Internal Input Termination MLFTM Manufacturing Guidelines Exposed Pad Application Notes HBW Solutions New Products and Termination Application Notes Data Sheet Link http://www.micrel.com/_PDF/HBW/sy89542u.pdf http://www.micrel.com/_PDF/HBW/sy89543u.pdf http://www.micrel.com/_PDF/HBW/sy89544u.pdf http://www.amkor.com/products/notespapers/MLF_appnote_0301.pdf http://www.micrel.com/product-info/products/sy89830u.shtml
February 2006
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Micrel, Inc.
SY89835U
Package Information
8-Pin MLFTM (MLF-8)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated.
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